There are many advantages to leverage the complementary metal-oxide-semiconductor (CMOS) process for microelectromechanical systems (MEMS). For passive radio frequency (RF) components, such as high-quality (high-Q) inductors using bulk micromachining to remove the silicon substrate enable to eliminate the substrate losses, parasitic effects and coupling interference, so that their self-resonant frequency and quality factor can be improved. Other micromachining devices, such as high-Q mechanical resonators, filters, RF low loss switches, tunable capacitors, and some representative components have also been designed and verified through CMOS-MEMS compatible processes. MEMS technologies offer the potential to build a plenty of miniaturized components on a same chip, and have various applications in that with high performance, multi-function, and also low cost. However, unlike the standard integrated circuit (IC) package where the circuits have rigid passivation, micromachined structures are restricted to the movable architecture and the absence of protective layer. For this reason, one of the main challenges in fabricating CMOS-MEMS multi-project wafers is to protect the released microstructures during dicing the wafers. Conventional dicing machine uses water to cool the rotating diamond blade during the dicing process, and thus damages the released micromachined devices. Other existing solutions such as hermetic-bonded glass/silicon cap, however, requires very smooth wafer surface, high bonding temperature, and high applied voltage. The above processes may damage the CMOS circuits that have been fabricated on the wafers. Besides, the complex procedure of those methods will also result in a low yield.
For an example, FIG. 1 shows a cross-sectional view of a CMOS-MEMS microstructure available from a multi-project wafer that was fabricated by TSMC 0.35 μm 2-poly 4-metal (2P4M) CMOS process and National Chip Implementation Center (CIC) CMOS post micromachining process. On a silicon substrate 10, a mechanical microstructure 12 is made of the metallization and dielectric layers of CMOS interconnections. The anisotropic/isotropic dry etching is employed to release the mechanical microstructure 12. Unlike the other portions on this wafer protected by nitride passivation layer 14 and metal layer 16, the released MEMS structure 12 is in contact with the environment, and easily affected by the post processing. Therefore, the safety and capability of the micromachined structure 12 tend to be critical.
Accordingly, there is a demand to prevent the MEMS structures on a wafer from destructive dicing process.